Voltage regulators are often used to provide a relatively constant voltage source to other electronic circuits. Some regulators are limited in their effectiveness in a particular application. For example, some regulators have a high "drop-out" voltage. A "drop-out" voltage is the minimum voltage difference between the input voltage and the output voltage that is necessary to maintain proper regulation. Large drop-out voltages result in wasted power, and raise the minimum power supply requirements for maintaining regulation.
A low-dropout regulator (hereinafter referred to as an "LDO regulator") is useful in applications where it is desired to maintain a regulated voltage that is sufficiently close to the input voltage. For example, LDO regulators are useful in battery-powered applications where the power supply voltage is exceedingly low.
A typical LDO regulator (100) is shown in FIG. 1. The LDO regulator (100) includes a PMOS transistor (MP10), a first resistor (R10), a second resistor (R11), and a voltage control block (110). The PMOS transistor (MP10) has a drain connected to an output terminal (VOUT), a gate connected to node N10, and a source connected to an input voltage (VIN). The first resistor (R10) is series connected between nodes the regulator output node (VREG) and node N11. The second resistor (R2) is series connected between nodes N11 and a circuit ground potential (GND). The voltage control block (110) has three input terminals (VIN, VREF, SENSE) and an output terminal (PCTL). In the voltage control block (110), the first input terminal (VIN) is connected to the input voltage (VIN), the second input terminal (VREF) is connected to a reference voltage potential (VREF), and the third input terminal (SENSE) is connected to node N10.
A load (ZL) is connected to the output terminal (VREG) of the LDO regulator (100). The LDO regulator (100) controls the gate of the PMOS transistor (MP10) to ensure that regulation of the output voltage (VREG) is maintained. The voltage control block (110) monitors the SENSE input terminal and controls the gate of the PMOS transistor (MP10) through the PCTL output terminal. Resistors R10 and R11 form a resistor divider that produces a signal that is related to the regulated output voltage (VREG). When the SENSE input terminal and the reference signal (VREF) are substantially the same, the LDO is properly maintaining regulation of the output voltage to the load (ZL).